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april 2007 hyb25dc512800b[e/f] HYB25DC512160B[e/f] 512-mbit double-data-rate sdram ddr sdram rohs compliant products internet data sheet rev. 1.2
we listen to your comments any information within this document that yo u feel is wrong, unclear or missing at all? your feedback will help us to continuous ly improve the quality of this document. please send your proposal (including a reference to this document) to: techdoc@qimonda.com internet data sheet hyb25dc512[80/16]0b[e/f] double-data-rate sdram qag_techdoc_rev400 / 3.2 qag / 2006-08-07 2 04112007-fhbx-o8hd hyb25dc512800b[e/f], HYB25DC512160B[e/f] revision history: 2007-04, rev. 1.2 page subjects (major chang es since last revision) all adapted internet edition all editorial changes previous revision: 2006-09, rev. 1.11 all qimonda template update previous revision: 2006-09, rev. 1.1
internet data sheet rev. 1.2, 2007-04 3 04112007-fhbx-o8hd hyb25dc512[80/16]0b[e/f] double-data-rate sdram 1overview this chapter lists all main features of the product fa mily hyb25dc512[80/16]0b[e/f] and the ordering information. 1.1 features ? double data rate architecture: tw o data transfers per clock cycle ? bidirectional data strobe (dqs) is transmitted and received with data, to be used in capturing data at the receiver ? dqs is edge-aligned with data for reads and is center-aligned with data for writes ? differential clock inputs (ck and ck ) ? four internal banks for concurrent operation ? data mask (dm) for write data ? dll aligns dq and dqs transitions with ck transitions ? commands entered on each positive ck edge; data and data mask referenced to both edges of dqs ? burst lengths: 2, 4, or 8 ? cas latency: 1.5 (ddr200 only), 2, 2.5, 3 ? auto precharge option for each burst access ? auto refresh and self refresh modes ? ras-lockout supported t rap = t rcd ?7.8 s maximum average periodic refresh interval ? 2.5 v (sstl_2 compatible) i/o ? v ddq = 2.5 v 0.2 v (ddr200, ddr266, ddr333); v ddq = 2.6 v 0.1 v (ddr400b) ? v dd = 2.5 v 0.2 v (ddr200, ddr266, ddr333); v dd = 2.6 v 0.1 v (ddr400b) ? standard temperature range (0 c - +70 c) ? pg-tsopii-66 and pg-tfbga-60 packages ?rohs 1) compliant product types available (green product) table 1 performance 1) rohs compliant product: restriction of the use of certain hazar dous substances (rohs) in el ectrical and electronic equipment as defined in the directive 2002/95/ec issued by the european parliament and of the council of 27 january 2003. these substances include m ercury, lead, cadmium, hexavalent chromium, polybro minated biphenyls and polybrominated biphenyl ethers. product type speed code ?5 ?6 unit speed grade component ddr400b ddr333 ? max. clock frequency @cl3 f ck3 200 166 mhz @cl2.5 f ck2.5 166 166 mhz @cl2 f ck2 133 133 mhz
internet data sheet rev. 1.2, 2007-04 4 04112007-fhbx-o8hd hyb25dc512[80/16]0b[e/f] double-data-rate sdram 1.2 description the 512-mbit double-data-rate sdram is a high-speed cmos, dynamic random-access memory containing 536,870,912 bits. it is internally configured as a quad-bank dram. the 512-mbit double-data-rate sdram uses a double-data-rate architecture to achieve high-speed operation. the double data rate architecture is essentially a 2n prefetch architecture with an interface designed to transfer two data words per clock cycle at the i/o pins. a single read or write access for the 512-mbit double-data-rate sdram effectively consists of a single 2n -bit wide, one clock cycle data transfer at the internal dram core and two corresponding n-bit wide, one-half-clock-cycle data transfers at the i/o pins. a bidirectional data strobe (dqs) is transmitted externally, along with data, for use in data capt ure at the receiver. dqs is a strobe transmitted by the ddr sdram during reads and by th e memory controller during wr ites. dqs is edge-aligned with data for reads and center-aligned with data for writes. the 512-mbit double-data-rate sdram operates from a differential clock (ck and ck ; the crossing of ck going high and ck going low is referred to as the positive edge of ck). co mmands (address and control signal s) are registered at every positive edge of ck. input data is registered on both edges of dqs, and output data is refe renced to both edges of dqs, as well as to both edges of ck. read and write accesses to the ddr sdra m are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. accesses begin with the registration of an active command, which is then followed by a read or write command. the addr ess bits registered coincident with the active command are used to select the bank and row to be accessed. the address bits registered coincident with the read or write command are used to select the bank and the starting column location for the burst access. the ddr sdram provides for programmable read or write burst lengths of 2, 4 or 8 locations. an auto precharge function may be enabled to provide a self-timed row pr echarge that is initiated at the end of the burst acce ss. as with standard sdrams, the pipelined, multibank architecture of ddr sdrams allows for concurrent operation, ther eby providing high effective bandwidth by hiding row precharge and activation time. an auto refresh mode is provided along with a power-saving power-down mode. all in puts are compatible with the industry standard for sstl_2. all outputs are sstl_2, class ii compatible. note: the functionality described and the timi ng specifications included in this dat a sheet are for the dll enabled mode of operation.
internet data sheet rev. 1.2, 2007-04 5 04112007-fhbx-o8hd hyb25dc512[80/16]0b[e/f] double-data-rate sdram table 2 ordering information for lead-free products (rohs compliant) product type 1)2) 1) hyb : designator for memory components; 25dc: ddr sdrams at v ddq = 2.5 v; 512: 512 mbit density; 800/160: product variations 8 and 16; b: die revision; l: low power (available on request); f/c/e/t: package type fbga (lead & halogen free), fbga (lead c ontaining), tsop (lead & halogen free), and tsop (lead containing ). 2) please check with your qimonda representat ive that leadtime and availability of your preferred device type and version meet y our project requirements. organization cas-rcd-rp latencies clock (mhz) speed package note hyb25dc512800be?5 8 3-3-3 200 ddr400b pg-tsopii-66 3) 3) rohs compliant product: restriction of the use of certain hazar dous substances (rohs) in el ectrical and electronic equipment as defined in the directive 2002/95/ec issued by the european parliament and of the council of 27 january 2003. these substances include m ercury, lead, cadmium, hexavalent chromium, polybro minated biphenyls and polybrominated biphenyl ethers. HYB25DC512160Be?5 16 hyb25dc512800be?6 8 2.5-3-3 166 ddr333 hyb25dc512800bel?6 8 HYB25DC512160Be?6 16 HYB25DC512160Bel?6 16 hyb25dc512800bf?5 8 3-3-3 200 ddr400b pg-tfbga-60 HYB25DC512160Bf?5 16 hyb25dc512800bf?6 8 2.5-3-3 166 ddr333 HYB25DC512160Bf?6 16
internet data sheet rev. 1.2, 2007-04 6 04112007-fhbx-o8hd hyb25dc512[80/16]0b[e/f] double-data-rate sdram 2 configuration this chapter contains the chip configuration. 2.1 configuration of pg-tsopii-66 the ball configuration of a ddr s dram is listed by function in table 3 . the abbreviations used in the pin#/buffer# column are explained in table 4 and table 5 respectively. the chip numbering for tsop is depicted in figure 1 . table 3 ball configuration ball#/pin# name pin type buffer type function clock signals 45 ck i sstl clock signal 46 ck i sstl complementary clock signal 44 cke i sstl clock enable control signals 23 ras i sstl row address strobe 22 cas i sstl column address strobe 21 we i sstl write enable 24 cs i sstl chip select address signals 26 ba0 i sstl bank address bus 2:0 27 ba1 i sstl 29 a0 i sstl address bus 11:0 30 a1 i sstl 31 a2 i sstl 32 a3 i sstl 35 a4 i sstl 36 a5 i sstl 37 a6 i sstl 38 a7 i sstl 39 a8 i sstl 40 a9 i sstl 28 a10 i sstl ap i sstl 41 a11 i sstl
internet data sheet rev. 1.2, 2007-04 7 04112007-fhbx-o8hd hyb25dc512[80/16]0b[e/f] double-data-rate sdram table 4 abbreviations for pin type table 5 abbreviations for buffer type 42 a12 i sstl address signal 12 note: module based on 256 mbit or larger dies nc nc ? note: module based on 128 mbit or smaller dies 17 a13 i sstl address signal 13 note: 1 gbit based module nc nc ? note: module based on 512 mbit or smaller dies power supplies 49 v ref ai ? i/o reference voltage 3, 9, 15, 55, 61 v ddq pwr ? i/o driver power supply 1, 18, 33 v dd pwr ? power supply 6, 12, 52, 58, 64 v ssq pwr ? power supply 34 v ss pwr ? power supply abbreviation description i standard input-only pin. digital levels o output. digital levels i/o i/o is a bidirectio nal input/output signal ai input. analog levels pwr power gnd ground nc not connected abbreviation description sstl serial stub terminalted logic (sstl2) lv-cmos low voltage cmos cmos cmos levels od open drain. the corresponding pin has 2 operat ional states, active low and tristate, and allows multiple devices to share as a wire-or ball#/pin# name pin type buffer type function
internet data sheet rev. 1.2, 2007-04 8 04112007-fhbx-o8hd hyb25dc512[80/16]0b[e/f] double-data-rate sdram figure 1 chip configuration pg-tsopii-66 033' 9 '' '4 9 ''4 9 664 '4 '4 9 ''4 '4 '4 '4 '4 9 664 '4 9 ''4 1& /'46 1&$ 9 '' 1& /'0 :( &$6 5$6 &6 1& %$ %$ $$3 $ $ $ $ 9 '' 9 '' '4 9 ''4 9 664 1& '4 9 ''4 1& '4 1& '4 9 664 1& 9 ''4 1& 1& 1&$ 9 '' 1& 1& :( &$6 5$6 &6 1& %$ %$ $$3 $ $ $ $ 9 '' 9 66 '4 9 664 9 ''4 '4 '4 9 664 '4 '4 '4 '4 9 ''4 '4 9 664 1& 8'46 1& 9 5() 8'0 &. &. &.( 1& 1&$ $ $ $ $ $ $ $ 9 66 9 66 9 66 '4 9 664 9 ''4 1& '4 9 664 1& '4 1& '4 9 ''4 1& 9 664 1& '46 1& 9 5() '0 &. &. &.( 1& 1&$ $ $ $ $ $ $ $ 9 66 9 66 [ [
internet data sheet rev. 1.2, 2007-04 9 04112007-fhbx-o8hd hyb25dc512[80/16]0b[e/f] double-data-rate sdram 2.2 configuration of pg-tfbga-60 the ball configuration of a ddr s dram is listed by function in table 6 . the abbreviations used in the pin#/buffer# column are explained in table 7 and table 8 respectively. table 6 ball configuration ball#/pin# name pin type buffer type function clock signals g2 ck1 i sstl clock signal g3 ck1 i sstl complementary clock signal h3 cke i sstl clock enable control signals h7 ras i sstl row address strobe g8 cas i sstl column address strobe g7 we i sstl write enable h8 cs i sstl chip select address signals j8 ba0 i sstl bank address bus 2:0 j7 ba1 i sstl k7 a0 i sstl address bus 12:0 l8 a1 i sstl l7 a2 i sstl m8 a3 i sstl m2 a4 i sstl l3 a5 i sstl l2 a6 i sstl k3 a7 i sstl k2 a8 i sstl j3 a9 i sstl k8 a10 i sstl ap i sstl j2 a11 i sstl h2 a12 i sstl
internet data sheet rev. 1.2, 2007-04 10 04112007-fhbx-o8hd hyb25dc512[80/16]0b[e/f] double-data-rate sdram data signals 8 organization a8 dq0 i/o sstl data signal bus 7:0 b7 dq1 i/o sstl c7 dq2 i/o sstl d7 dq3 i/o sstl d3 dq4 i/o sstl c3 dq5 i/o sstl b3 dq6 i/o sstl a2 dq7 i/o sstl data strobe 8 organization e3 dqs i/o sstl data strobe data mask 8 organization f3 dm i sstl data mask data signals 16 organization a8 dq0 i/o sstl data signal 15:0 b9 dq1 i/o sstl b7 dq2 i/o sstl c9 dq3 i/o sstl c7 dq4 i/o sstl d9 dq5 i/o sstl d7 dq6 i/o sstl e9 dq7 i/o sstl e1 dq8 i/o sstl d3 dq9 i/o sstl d1 dq10 i/o sstl c3 dq11 i/o sstl c1 dq12 i/o sstl b3 dq13 i/o sstl b1 dq14 i/o sstl a2 dq15 i/o sstl data strobe 16 organization e3 udqs i/o sstl data strobe upper byte e7 ldqs i/o sstl data strobe lower byte data mask 16 organization f3 udm i sstl data mask upper byte f7 ldm i sstl data mask lower byte power supplies f1 v ref ai ? i/o reference voltage a9, b2, c8, d2, e8 v ddq pwr ? i/o driver power supply ball#/pin# name pin type buffer type function
internet data sheet rev. 1.2, 2007-04 11 04112007-fhbx-o8hd hyb25dc512[80/16]0b[e/f] double-data-rate sdram table 7 abbreviations for pin type table 8 abbreviations for buffer type a7, f8, m7 v dd pwr ? power supply a1, b8, c2, d8, e2 v ssq pwr ? power supply a3, f2, m3 v ss pwr ? power supply not connected 8 organization b1, b9, c1, c9, d1, d9, e1, e7, e9, f7, f9 nc nc ? not connected not connected 16 organization f9 nc nc ? not connected abbreviation description i standard input-only pin. digital levels o output. digital levels i/o i/o is a bidirectio nal input/output signal ai input. analog levels pwr power gnd ground nc not connected abbreviation description sstl serial stub terminalted logic (sstl2) lv-cmos low voltage cmos cmos cmos levels od open drain. the corresponding pin has 2 operat ional states, active low and tristate, and allows multiple devices to share as a wire-or ball#/pin# name pin type buffer type function
internet data sheet rev. 1.2, 2007-04 12 04112007-fhbx-o8hd hyb25dc512[80/16]0b[e/f] double-data-rate sdram figure 2 pin configuration for x8 orga nization, pg-tfbga-60, top view 033' &$6 &6 9 664 '46 &. 1& 1& 1& 1& 9 5() '4 9 ''4 9 664 9 ''4 9 664 9 66 $ $ $ $ $ &. &.( $ $ $ 9 66 '0 '4 '4 '4 9 66 :( 5$6 %$ $ $ 9 '' '4 '4 '4 9 '' 1& 1& '4 9 664 9 ''4 9 664 9 '' %$ $$3 $ $ 9 ''4 9 ''4 1& 1& 1& 1& 1& $ % & ' ) * + - ( / 0 . [
internet data sheet rev. 1.2, 2007-04 13 04112007-fhbx-o8hd hyb25dc512[80/16]0b[e/f] double-data-rate sdram figure 3 pin configuration for x16 orga nization, pg-tfbga-60, top view 033' 8'46 &. '4 '4 '4 '4 9 5() '4 9 ''4 9 664 9 ''4 9 664 9 66 $ $ $ $ $ &.( $ $ $ 9 66 8'0 '4 '4 '4 9 66 $ % & ' ) * + - ( / 0 . [ &. %$ $ $ 9 '' '4 '4 '4 9 '' /'46 /'0 '4 9 664 9 ''4 9 664 9 '' %$ $$3 $ $ 9 ''4 9 ''4 '4 '4 '4 '4 1& :( &$6 5$6 &6 9 664
internet data sheet rev. 1.2, 2007-04 14 04112007-fhbx-o8hd hyb25dc512[80/16]0b[e/f] double-data-rate sdram 3 functional description table 9 mode register definition field bits type 1) 1) w = write only register bit description bl [2:0] w burst length number of sequential bits per dq related to one read/write command. note: all other bit combinations are reserved. 001 b 2 010 b 4 011 b 8 bt 3 burst type see table 10 for internal address sequence of low order address bits. 0 sequential 1 interleaved cl [6:4] cas latency number of full clocks from read command to first data valid window. note: all other bit combinations are reserved. 010 b 2 011 b 3 110 b 2.5 101 b 1.5 note: cl = 1.5 for ddr200 components only mode [12:7] operating mode note: all other bit combinations are reserved. 000000 normal operation without dll reset 000010 normal operation with dll reset 03%7 %$ %$ $ $ $ $ $ $ $ $ $ $ $ $ $ 02'( %/ &/ %7 uhjdggu zzzz
internet data sheet rev. 1.2, 2007-04 15 04112007-fhbx-o8hd hyb25dc512[80/16]0b[e/f] double-data-rate sdram table 10 burst definition notes 1. for a burst length of two, a1-ai selects the two-data-el ement block; a0 selects the first access within the block. 2. for a burst length of four, a2-ai sele cts the four-data-elem ent block; a0-a1 selects the first access within the block. 3. for a burst length of eight, a3-ai selects the eight-data- element block; a0-a2 selects the first access within the block. 4. whenever a boundary of the block is reached within a give n sequence above, the following access wraps within the block. burst length starting column address order of accesses within a burst a2 a1 a0 type = sequential type = interleaved 200-10-1 11-0 1-0 4 0 0 0-1-2-3 0-1-2-3 0 1 1-2-3-0 1-0-3-2 1 0 2-3-0-1 2-3-0-1 1 1 3-0-1-2 3-2-1-0 8 0000-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7 0011-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6 0102-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5 0113-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4 1004-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3 1015-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2 1106-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1 1117-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0
internet data sheet rev. 1.2, 2007-04 16 04112007-fhbx-o8hd hyb25dc512[80/16]0b[e/f] double-data-rate sdram table 11 extended mode register table 12 truth table 1a: commands field bits type 1) 1) w = write only register bit description dll 0w dll status 0 b enabled 1 b disabled ds 1 drive strength 0 b normal 1 b weak mode [12:3] operating mode 00000000000 b normal operation notes 1. a2 must be 0 to provide compatibility with early ddr devices 2. all other bit combi nations are reserved. name (function) cs ras cas we address mne note deselect (nop) h x x x x nop 1)2) 1) cke is high for all commands shown exceptself refresh. v ref must be maintained during self refresh operation. 2) deselect and nop are functionally interchangeable. no operation (nop) l h h h x nop 1)2) active (select bank and activate row) l l h h bank/row act 1)3) 3) ba0-ba1 provide bank address and a0-a12 provide row address. read (select bank and column, and start read burst) l h l h bank/col read 1)4) 4) ba0, ba1 provide bank address; a0-a9 (x16 device); a0 - a9, a1 1 (x8 device)provide column address ; a10 high enables the auto precharge feature (nonpersistent), a10 low disables the auto precharge feature. write (select bank and column, and start write burst) l h l l bank/col write 1)4) burst terminate l h h l x bst 1)5) 5) applies only to read bursts with auto precharge disabled; th is command is undefined (and should not be used) for read bursts with auto precharge enabled or for write bursts. precharge (deactivate row in bank or banks) l l h l code pre 1)6) 6) a10 low: ba0, ba1 determine which bank is precharged. a10 high: all banks are precharged and ba0, ba1 are ?don?t care?. auto refresh or self refresh (e nter self refresh mode) l l l h x ar/sr 1)7)8) 7) this command is auto refresh if cke is high; self refresh if cke is low. mode register set l l l l op-code mrs 1)9) 03%7 %$ %$ $ $ $ $ $ $ $ $ $ $ $ $ $ 02'( '// '6 uhjdggu zz zz
internet data sheet rev. 1.2, 2007-04 17 04112007-fhbx-o8hd hyb25dc512[80/16]0b[e/f] double-data-rate sdram table 13 truth table 1b: dm operation table 14 truth table 2: clock enable (cke) 1. cken is the logic state of cke at clock edge n: ck e n-1 was the state of cke at the previous clock edge. 2. current state is the state of the ddr sdram immediately prior to clock edge n. 3. command n is the command registered at clock edge n, and action n is a result of command n. 4. all states and sequences not shown are illegal or reserved. 8) internal refresh counter controls row and bank addressi ng; all inputs and i/os are ?don?t care? except for cke. 9) ba0, ba1 select either the base or the extended mode register ( ba0 = 0, ba1 = 0 selects mode register; ba0 = 1, ba1 = 0 selects extended mode register; other combinations of ba0-ba1 are reserv ed; a0-a12 provide the op-code to be written to the selected mo de register). name (function) dm dqs note write enable lvalid 1) 1) used to mask write data; provided coincident with the corresponding data. write inhibit hx 1) current state cke n-1 cken command n action n note previous cycle current cycle self refresh l l x maintain self-refresh 1) 1) v ref must be maintained during self refresh operation self refresh l h deselect or nop exit self-refresh 2) 2) deselect or nop commands should be issued on any clock edges occurri ng during the self refresh exit ( t xsnr ) period. a minimum of 200 clock cycles are needed before applying a read command to allow the dll to lock to the input clock. power down l l x maintain power-down ? power down l h deselect or nop exit power-down ? all banks idle h l deselect or nop precharge power-down entry ? all banks idle h l auto refresh self refresh entry ? bank(s) active h l deselect or nop active power-down entry ? h h see table 15 ??
internet data sheet rev. 1.2, 2007-04 18 04112007-fhbx-o8hd hyb25dc512[80/16]0b[e/f] double-data-rate sdram table 15 truth table 3: current state bank n - command to bank n (same bank) current state cs ras cas we command action note any h x x x deselect nop. continue previous operation. 1)2)3)4)5)6) 1) this table applies when cke n-1 was high and cke n is high (see table 14 and after t xsnr / t xsrd has been met (if the previous state was self refresh). 2) this table is bank-specific, ex cept where noted, i.e., the current state is for a specific bank and the commands shown are th ose allowed to be issued to that bank when in that state. exceptions are covered in the notes below. 3) current state definitions: idle: the bank has been precharged, and t rp has been met. row active: a row in the bank has been activated, and t rcd has been met. no data bursts/accesses and no register accesses are in progress. read: a read burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminat ed. write: a write burst has been initiated, with auto prec harge disabled, and has not yet terminated or been terminated. 4) the following states must not be interru pted by a command issued to the same bank. precharging: starts with registration of a precharge command and ends when t rp is met. once t rp is met, the bank is in the idle state. row activating: starts with registra tion of an active command and ends when t rcd is met. once t rcd is met, the bank is in the ?row active? state. read w/auto precharge enabled: starts with registration of a read command with auto precharge enabled and ends when t rp has been met. once t rp is met, the bank is in the idle state. write w/auto precharge enabled: starts with registrati on of a write command with auto precharge enabled and ends when t rp has been met. once t rp is met, the bank is in the idle state. deselect or nop commands, or allowable commands to the other bank should be issued on any clock edge occurring during these states . allowable commands to the other bank are determined by its current state and a ccording to table 16 . 5) the following states must not be interrupted by any executab le command; deselect or nop commands must be applied on each posi tive clock edge during these states. refreshing: starts with registration of an auto refresh command and ends when t rfc is met. once t rfc is met, the ddr sdram is in the ?all banks idle? state. accessing mode register: starts with registrati on of a mode register set command and ends when t mrd has been met. once t mrd is met, the ddr sdram is in the ?all banks idle? state. precharging all: starts with registration of a precharge all command and ends when t rp is met. once t rp is met, all banks is in the idle state. 6) all states and sequences not shown are illegal or reserved. l h h h no operation nop. continue previous operation. 1) to 6) idle l l h h active select and activate row 1) to 6) l l l h auto refresh ? 1) to 7) 7) not bank-specific; requires that all banks are idle. llllmode register set ? 1) to 7) row active l h l h read select column and start read burst 1) to 6), 8) 8) reads or writes listed in the command/action column include read s or writes with auto precharge enabled and reads or writes w ith auto precharge disabled. l h l l write select column and start write burst 1) to 6), 8) l l h l precharge deactivate row in bank(s) 1) to 6), 9) 9) may or may not be bank-specific; if al l/any banks are to be precharged, all/any must be in a valid state for precharging. read (auto precharge disabled) l h l h read select column and start new read burst 1) to 6), 8) l l h l precharge truncate read burst, start precharge 1) to 6), 9) l h h l burst terminate burst terminate 1) to 6), 10) 10) not bank-specific; burst terminate affects th e most recent read burst, regardless of bank. write (auto precharge disabled) l h l h read select column and start read burst 1) to 6), 8), 11) 11) requires appropriate dm masking. l h l l write select column and start write burst 1) to 6), 8) l l h l precharge truncate write burst, start precharge 1) to 6), 9), 11)
internet data sheet rev. 1.2, 2007-04 19 04112007-fhbx-o8hd hyb25dc512[80/16]0b[e/f] double-data-rate sdram table 16 truth table 4: current state bank n - command to bank m (different bank) current state cs ras cas we command action note any hxxxdeselect nop. continue previous operation. 1)2)3)4)5)6) 1) this table applies when cke n-1 was high and cke n is high (see table 14 : clock enable (cke) and after t xsnr / t xsrd has been met (if the previous state was self refresh). 2) this table describes alternate bank oper ation, except where noted, i.e., the current state is for bank n and the commands sho wn are those allowed to be issued to bank m (assuming t hat bank m is in such a state that the gi ven command is allowabl e). exceptions are co vered in the notes below. 3) current state definitions: idle: the bank has been precharged, and t rp has been met. row active: a row in the bank has been activated, and t rcd has been met. no data bursts/accesses and no register accesses are in progress. read: a read burst has been initiated, with auto prechar ge disabled, and has not yet terminated or been terminated. write: a write burst has been initiated, with auto prechar ge disabled, and has not yet terminated or been terminated. read with auto precharge enabled: see 10) . write with auto precharge enabled: see 10) . 4) auto refresh and mode register set commands may only be issued when all banks are idle. 5) a burst terminate command cannot be issued to another bank; it applies to the bank represented by the current state only. 6) all states and sequences not shown are illegal or reserved. l hhhno operation nop. continue previous operation. 1) to 6) idle xxxxany command otherwise allowed to bank m ? 1) to 6) row activating, active, or precharging l l h h active select and activate row 1) to 6) l h l h read select column and start read burst 1) to 7) 7) reads or writes listed in the command/action column include read s or writes with auto precharge enabled and reads or writes w ith auto precharge disabled. l h l l write select column and start write burst 1) to 7) llhlprecharge ? 1) to 6) read (auto precharge disabled) l l h h active select and activate row 1) to 6) l h l h read select column and start new read burst 1) to 7) llhlprecharge ? 1) to 6) write (auto precharge disabled) l l h h active select and activate row 1) to 6) l h l h read select column and start read burst 1) to 8) 8) requires appropriate dm masking. l h l l write select column and start new write burst 1) to 7) llhlprecharge ? 1) to 6) read (with auto precharge) l l h h active select and activate row 1) to 6) l h l h read select column and start new read burst 1) to 7), 9) l h l l write select column and start write burst 1) to 7), 9), 10) llhlprecharge ? 1) to 6) write (with auto precharge) l l h h active select and activate row 1) to 6) l h l h read select column and start read burst 1) to 7), 9) l h l l write select column and start new write burst 1) to 7), 9) llhlprecharge ? 1) to 6)
internet data sheet rev. 1.2, 2007-04 20 04112007-fhbx-o8hd hyb25dc512[80/16]0b[e/f] double-data-rate sdram table 17 truth table 5: concurrent auto precharge 9) concurrent auto precharge: this device supports ?concurrent auto precharge?. when a read with auto precharge or a write with auto precharge is enabled any command may follow to the other banks as long as that command does not interrupt the read or write dat a transfer and all other limitations apply (e.g. contenti on between read data and write data must be avoided). the minimum delay from a re ad or write command with auto precharge enable, to a command to a different banks is summarized in table 17 . 10) a write command may be applied after the completion of data output. from command to command (different bank) minimum delay with concurrent auto precharge support unit write w/ap read or read w/ap 1 + (bl/2) + t wtr t ck write to write w/ap bl/2 t ck precharge or activate 1 t ck read w/ap read or read w/ap bl/2 t ck write or write w/ap cl (rounded up) + bl/2 t ck precharge or activate 1 t ck
internet data sheet rev. 1.2, 2007-04 21 04112007-fhbx-o8hd hyb25dc512[80/16]0b[e/f] double-data-rate sdram 4 electrical characteristics this chapter describes the electrical characteristics. 4.1 operating conditions this chapter contains the operating conditions tables. table 18 absolute maximum ratings attention: stresses above the max. value s listed here may cause permanent damage to the device. exposure to absolute maximum rating conditions for extended periods may affect device reliability. maximum ratings are absolute ratings; exceeding only one of these values may cause irreversible damage to the integrated circuit. parameter symbol values unit note/ test condition min. typ. max. voltage on i/o pins relative to v ss v in , v out ?0.5 ? v ddq + 0.5 v ? voltage on inputs relative to v ss v in ?1 ? +3.6 v ? voltage on v dd supply relative to v ss v dd ?1 ? +3.6 v ? voltage on v ddq supply relative to v ss v ddq ?1 ? +3.6 v ? operating temperature (ambient) t a 0?+70 c? storage temperature (plastic) t stg ?55 ? +150 c? power dissipation (per sdram component) p d ?1? w? short circuit output current i out ?50? ma?
internet data sheet rev. 1.2, 2007-04 22 04112007-fhbx-o8hd hyb25dc512[80/16]0b[e/f] double-data-rate sdram table 19 input and output capacitances parameter symbol values unit note/ test condition min. typ. max. input capacitance: ck, ck c i1 2.0 ? 3.0 pf tsop 1) 1) these values are guaranteed by design and are tested on a sample base only. v ddq = v dd = 2.5 v 0.2 v, f = 100 mhz, t a = 25 c, v out(dc) = v ddq /2, v out (peak to peak) 0.2 v. unused pins are tied to ground. 1.5 ? 2.5 pf fbga 1) delta input capacitance c di1 ? ? 0.25 pf 1) input capacitance: all other input-only pins c i2 2.0 ? 3.0 pf tsop 1) 1.5 ? 2.5 pf fbga 1) delta input capacitance: all other input-only pins c dio ?? 0.5pf 1) input/output capacitance: dq, dqs, dm c io 4.0 ? 5.0 pf tsop 1)2) 2) dm inputs are grouped with i/o pins reflecting the fact that t hey are matched in loading to dq and dqs to facilitate trace ma tching at the board level. 3.5 ? 4.5 pf fbga 1)2) delta input/output capaci tance: dq, dqs, dm c dio ?? 0.5pf 1)
internet data sheet rev. 1.2, 2007-04 23 04112007-fhbx-o8hd hyb25dc512[80/16]0b[e/f] double-data-rate sdram table 20 electrical characteristics and dc operating conditions parameter symbol values unit note/ test condition 1) 1) 0 c t a 70 c; v ddq = 2.5 v 0.2 v, v dd = +2.5 v 0.2 v; min. typ. max. device supply voltage v dd 2.3 2.5 2.7 v f ck 166 mhz device supply voltage v dd 2.5 2.6 2.7 v f ck > 166 mhz 2) 2) ddr400 conditions apply for all clock frequencies above 166 mhz output supply voltage v ddq 2.3 2.5 2.7 v f ck 166 mhz 3) 3) under all conditions, v ddq must be less than or equal to v dd . output supply voltage v ddq 2.5 2.6 2.7 v f ck >166mhz 2)3) supply voltage, i/o supply voltage v ss , v ssq 0?0v? input reference voltage v ref 0.49 v ddq 0.5 v ddq 0.51 v ddq v 4) 4) peak to peak ac noise on v ref may not exceed 2% v ref.dc . v ref is also expected to tr ack noise variations in v ddq . i/o termination voltage (system) v tt v ref ? 0.04 ? v ref + 0.04 v 5) 5) v tt is not applied directly to the device. v tt is a system supply for signal termination resistors, is expected to be set equal to v ref , and must track variations in the dc level of v ref . input high (logic1) voltage v ih(dc) v ref + 0.15 ? v ddq + 0.3 v 6) 6) inputs are not recognized as valid until v ref stabilizes. input low (logic0) voltage v il(dc) ? 0.3 ? v ref ? 0.15 v 6) input voltage level, ck and ck inputs v in(dc) ? 0.3 ? v ddq + 0.3 v 6) input differential voltage, ck and ck inputs v id(dc) 0.36 ? v ddq + 0.6 v 6)7) 7) v id is the magnitude of the difference between the input level on ck and the input level on ck . vi-matching pull-up current to pull-down current v i ratio 0.71 ? 1.4 ? 8) 8) the ratio of the pull-up current to the pull-down current is specified for the same temperature and voltage, over the entire temperature and voltage range, for device drain to source voltage from 0.25 to 1. 0 v. for a given output, it represents the maximum difference b etween pull-up and pull-down drivers due to process variation. input leakage current i i ?2 ? 2 a any input 0 v v in v dd ; all other pins not under test = 0 v 9) 9) values are shown per pin. output leakage current i oz ?5 ? 5 a dqs are disabled; 0 v v out v ddq 9) output high current, normal strength driver i oh ? ? ?16.2 ma v out = 1.95 v output low current, normal strength driver i ol 16.2 ? ? ma v out = 0.35 v
internet data sheet rev. 1.2, 2007-04 24 04112007-fhbx-o8hd hyb25dc512[80/16]0b[e/f] double-data-rate sdram 4.2 ac characteristics notes 1-5 apply to the following tables; electrical characte ristics and dc operating conditi ons, ac operating conditions, i dd specifications and conditions, and el ectrical characteristics and ac timing. notes 1. all voltages referenced to v ss . 2. tests for ac timing, i dd , and electrical, ac and dc characteristics, may be conducted at nominal re ference/supply voltage levels, but the related specifications and device oper ation are guaranteed for the full voltage range specified. 3. figure 4 represents the timing reference load used in defining the re levant timing parameters of the part. it is not intended to be either a precise representation of the typical system environm ent nor a depiction of the ac tual load presented by a production tester. system designers will use ibis or other simula tion tools to correlate the ti ming reference load to a system environment. manufacturers will correlate to their production test conditions (generally a coaxial transmission line terminated at the tester electronics). 4. ac timing and i dd tests may use a v il to v ih swing of up to 1.5 v in the test environ ment, but input timing is still referenced to v ref (or to the crossi ng point for ck, ck ), and parameter spec ifications are guaranteed for t he specified ac input levels under normal use conditions. the minimum slew rate for the input signals is 1 v/ns in the range between v il(ac) and v ih(ac) . 5. the ac and dc input level specifications are as defined in the sstl_2 standard (i.e . the receiver effectively switches as a result of the signal crossing the ac input level, and remain s in that state as long as the signal does not ring back above (below) the dc input low (high) level). 6. for system characteristics like setup & holdtime derating for slew rate, i/o delta rise/ fall derating, ddr sdram slew rate standards, overshoot & undershoot specification and clamp v - i characteristics see the latest industry specification for ddr components. figure 4 ac output load circuit diagram / timing reference load 50 : timing reference point output ( v out ) 30 pf v tt
internet data sheet rev. 1.2, 2007-04 25 04112007-fhbx-o8hd hyb25dc512[80/16]0b[e/f] double-data-rate sdram table 21 ac operating conditions table 22 ac timing - absolute specifications parameter symbol values unit note/ test condition min. max. input high (logic 1) voltage, dq, dqs and dm signals v ih(ac) v ref + 0.31 ? v 1) 2)3) 1) v ddq = 2.5 v 0.2 v, v dd = +2.5 v 0.2 v (ddr200 - ddr333); v ddq = 2.6 v 0.1 v, v dd = +2.6 v 0.1 v (ddr400); 0 c t a 70 c 2) input slew rate = 1 v/ns. 3) inputs are not recognized as valid until v ref stabilizes. input low (logic 0) voltage, dq, dqs and dm signals v il(ac) ? v ref ? 0.31 v 1)2)3) input differential voltage, ck and ck inputs v id(ac) 0.7 v ddq + 0.6 v 1)2)3)4) 4) v id is the magnitude of the difference between the input level on ck and the input level on ck . input closing point voltage, ck and ck inputs v ix(ac) 0.5 v ddq ? 0.2 0.5 v ddq + 0.2 v 1)2)3)5) 5) the value of v ix is expected to equal 0.5 v ddq of the transmitting device and must track variations in the dc level of the same. parameter symbol ?5 ?6 unit note/ test condition 1) ddr400b ddr333 min. max. min. max. dq output access time from ck/ck t ac ?0.5 +0.5 ?0.7 +0.7 ns 2)3)4)5) ck high-level width t ch 0.45 0.55 0.45 0.55 t ck 2)3)4)5) clock cycle time t ck 5 8 6 12 ns cl = 3.0 2)3)4)5) 6 12 6 12 ns cl = 2.5 2)3)4)5) 7.5 12 7.5 12 ns cl = 2.0 2)3)4)5) ck low-level width t cl 0.45 0.55 0.45 0.55 t ck 2)3)4)5) auto precharge write recovery + precharge time t dal ( t wr / t ck )+( t rp / t ck ) t ck 2)3)4)5)6) dq and dm input hold time t dh 0.4 ? 0.45 ? ns 2)3)4)5) dq and dm input pulse width (each input) t dipw 1.75 ? 1.75 ? ns 2)3)4)5)6) dqs output access time from ck/ck t dqsck ?0.6 +0.6 ?0.6 +0.6 ns 2)3)4)5) dqs input low (high) pulse width (write cycle) t dqsl,h 0.35 ? 0.35 ? t ck 2)3)4)5) dqs-dq skew (dqs and associated dq signals) t dqsq ? +0.40 ? +0.45 ns tsop 2)3)4)5) dqs-dq skew (dqs and associated dq signals) t dqsq ? +0.40 ? +0.40 ns fbga 2)3)4)5) write command to 1 st dqs latching transition t dqss 0.72 1.25 0.75 1.25 t ck 2)3)4)5)
internet data sheet rev. 1.2, 2007-04 26 04112007-fhbx-o8hd hyb25dc512[80/16]0b[e/f] double-data-rate sdram dq and dm input setup time t ds 0.4 ? 0.45 ? ns 2)3)4)5) dqs falling edge hold time from ck (write cycle) t dsh 0.2 ? 0.2 ? t ck 2)3)4)5) dqs falling edge to ck setup time (write cycle) t dss 0.2 ? 0.2 ? t ck 2)3)4)5) clock half period t hp min. ( t cl , t ch )? min. ( t cl , t ch )? ns 2)3)4)5) data-out high-impedance time from ck/ck t hz ? +0.7 ? +0.7 ns 2)3)4)5)7) address and control input hold time t ih 0.6 ? 0.75 ? ns fast slew rate 3)4)5)6)8) 0.7 ? 0.8 ? ns slow slew rate 3)4)5)6)8) control and addr. input pulse width (each input) t ipw 2.2 ? 2.2 ? ns 2)3)4)5)9) address and control input setup time t is 0.6 ? 0.75 ? ns fast slew rate 3)4)5)6)8) 0.7 ? 0.8 ? ns slow slew rate 3)4)5)6)8) data-out low-impedance time from ck/ck t lz ?0.7 +0.70 ?0.70 +0.70 ns 2)3)4)5)7) mode register set command cycle time t mrd 2?2? t ck 2)3)4)5) dq/dqs output hold time from dqs t qh t hp ? t qhs ? t hp ? t qhs ?ns 2)3)4)5) data hold skew factor t qhs ? +0.50 ? +0.55 ns tsopii 2)3)4)5) data hold skew factor t qhs ? +0.50 ? +0.50 ns tfbga 2)3)4)5) active to autoprecharge delay t rap t rcd ? t rcd ?ns 2)3)4)5) active to precharge command t ras 40 70e+3 42 70e+3 ns 2)3)4)5) active to active/auto-refresh command period t rc 55 ? 60 ? ns 2)3)4)5) active to read or write delay t rcd 15 ? 18 ? ns 2)3)4)5) average periodic refresh interval t refi ? 7.8 ? 7.8 s 2)3)4)5)8) precharge command period t rp 15 ? 18 ? ns 2)3)4)5) read preamble t rpre 0.9 1.1 0.9 1.1 t ck 2)3)4)5) read postamble t rpst 0.40 0.60 0.40 0.60 t ck 2)3)4)5) active bank a to active bank b command t rrd 10 ? 12 ? ns 2)3)4)5) write preamble t wpre max. (0.25 t ck , 1.5 ns) ?0.25 t ck ?ns 2)3)4)5) write preamble setup time t wpres 0?0?ns 2)3)4)5)10) parameter symbol ?5 ?6 unit note/ test condition 1) ddr400b ddr333 min. max. min. max.
internet data sheet rev. 1.2, 2007-04 27 04112007-fhbx-o8hd hyb25dc512[80/16]0b[e/f] double-data-rate sdram write postamble t wpst 0.40 0.60 0.40 0.60 t ck 2)3)4)5)11) write recovery time t wr 15 ? 15 ? ns 2)3)4)5) internal write to read command delay t wtr 2?1? t ck 2)3)4)5) exit self-refresh to non-read command t xsnr 75 ? 75 ? ns 2)3)4)5) exit self-refresh to read command t xsrd 200 ? 200 ? t ck 2)3)4)5) 1) 0 c t a 70 c; v ddq = 2.5 v 0.2 v, v dd = +2.5 v 0.2 v (ddr333); v ddq = 2.6 v 0.1 v, v dd = +2.6 v 0.1 v (ddr400) 2) input slew rate 1 v/ns for ddr400, ddr333 3) the ck/ck input reference level (for timing reference to ck/ck ) is the point at which ck and ck cross: the input reference level for signals other than ck/ck , is v ref . ck/ck slew rate are 1.0 v/ns. 4) inputs are not recognized as valid until v ref stabilizes. 5) the output timing reference level, as measured at the timing reference point indicated in ac characteristics (note 3) is v tt . 6) for each of the terms, if not already an integer, round to the next highest integer. t ck is equal to the actual system clock cycle time. 7) t hz and t lz transitions occur in the same access time windows as valid data transitions. these parameters are not referred to a specific voltage level, but specify when the device is no longer driving (hz), or begins driving (lz). 8) fast slew rate 1.0 v/ns , slow slew rate 0.5 v/ns and < 1 v/ns for command/address and ck & ck slew rate > 1.0 v/ns, measured between v ih(ac) and v il(ac) . 9) these parameters guarantee device timing, but th ey are not necessarily tested on each device. 10) the specific requirement is that dqs be valid (high,low, or some point on a valid transition) on or before this ck edge. a v alid transition is defined as monotonic and meeting the input slew rate specificationsof the device. w hen no writes were previously in progress on the bus, dqs will be transitioni ng from hi-z to logic low. if a previous write wa s in progress, dqs could be high, low at this time , depending on t dqss . 11) the maximum limit for this parameter is not a device limit. the device operates with a greater value for this parameter, but system performance (bus turnaround) degrades accordingly. parameter symbol ?5 ?6 unit note/ test condition 1) ddr400b ddr333 min. max. min. max.
internet data sheet rev. 1.2, 2007-04 28 04112007-fhbx-o8hd hyb25dc512[80/16]0b[e/f] double-data-rate sdram table 23 i dd conditions parameter symbol operating current: one bank; active/ precharge; t rc = t rcmin ; t ck = t ckmin ; dq, dm, and dqs inputs changing once per clock cycle ; address and control inputs changing once every two clock cycles. i dd0 operating current: one bank; active/read/precharge; burst = 4; refer to the following page for detailed test conditions. i dd1 precharge power-down standby current: all banks idle; power-down mode; cke v ilmax ; t ck = t ckmin i dd2p precharge floating standby current: cs v ihmin , all banks idle; cke v ihmin ; t ck = t ckmin , address and other c ontrol inputs ch anging once per clock cycle, v in = v ref for dq, dqs and dm. i dd2f precharge quiet standby current: cs v ihmin , all banks idle; cke v ihmin ; t ck = t ckmin , address and other control inputs stable at v ihmin or v ilmax ; v in = v ref for dq, dqs and dm. i dd2q active power-down standby current: one bank active; power-down mode; cke v ilmax ; t ck = t ckmin ; v in = v ref for dq, dqs and dm. i dd3p active standby current: one bank active; cs v ihmin ; cke v ihmin ; t rc = t rasmax ; t ck = t ckmin ; dq, dm and dqs inputs changing twice per clock cycle; address and control inputs changing once per clock cycle i dd3n operating current: one bank active; burst = 2; reads; continuo us burst; address and control inputs changing once per clock cycle; 50 % of data outputs changing on every clock edg e; cl = 2 for ddr200 and ddr266a, cl = 3 for ddr333; t ck = t ckmin ; i out =0ma i dd4r operating current: one bank active; burst = 2; writes; continuous burst; address and control inputs changing once per clock cycle; 50 % of data outputs changing on every clock edg e; cl = 2 for ddr200 and ddr266a, cl = 3 for ddr333; t ck = t ckmin i dd4w auto-refresh current: t rc = t rfcmin , burst refresh i dd5 self-refresh current: cke 0.2 v; external clock on; t ck = t ckmin i dd6 operating current: four bank; four bank interleaving with bl = 4; refer to the following page for detailed test conditions. i dd7
internet data sheet rev. 1.2, 2007-04 29 04112007-fhbx-o8hd hyb25dc512[80/16]0b[e/f] double-data-rate sdram table 24 i dd specification symbol ?5 ?6 unit note 1) 1) test conditions : v dd = 2.7 v, t a = 10 c ddr400b ddr333 i dd0 80 75 ma 8 2)3) 2) i dd specifications are tested after the device is properly initialized and measured at 200 mhz. 3) input slew rate = 1 v/ns. 100 90 ma 16 3) i dd1 90 85 ma 8 3) 115 105 ma 16 3) i dd2p 1.7 1.6 ma 3) i dd2f 30 25 ma 3) i dd2q 19 17 ma 3) i dd3p 12 11 ma 3) i dd3n 39 35 ma 8 3) 42 37 ma 16 3) i dd4r 85 77 ma 8 3) 120 105 ma 16 3) i dd4w 90 81 ma 8 3) 125 110 ma 16 3) i dd5 205 185 ma 3) i dd6 2.8 2.7 ma 4) 4) enables on-chip refresh and address counters. 2.5 2.5 ma low power i dd7 260 234 ma 8 3) 285 255 ma 16 3)
internet data sheet rev. 1.2, 2007-04 30 04112007-fhbx-o8hd hyb25dc512[80/16]0b[e/f] double-data-rate sdram 5 package dimensions the chapter describes the package types used for this product family. figure 5 package outline pg-tsopii-66 notes 1. drawing according to iso 8015 2. dimensions in mm 3. general tolerances +/- 0.15 ' r h v q r w l q f o x g h s o d v w l f r u p h w d o s u r w u x v l r q r i p d [ s h u v l g h ' r h v q r w l q f o x g h s o d v w l f s u r w u x v l r q r i p d [ s h u v l g h ' r h v q r w l q f o x g h g d p e d u s u r w u x v l r q r i p d [ , q g h [ 0 d u n l q j 0 $; ? 0 $; ? [ ? ? ? ? ? ? ? [ 0 [ ? ? ? ?
internet data sheet rev. 1.2, 2007-04 31 04112007-fhbx-o8hd hyb25dc512[80/16]0b[e/f] double-data-rate sdram figure 6 package outline p(g)-tfbga-60 notes 1. drawing according to iso 8015 2. dimensions in mm 3. general tolerances +/- 0.15 $ i e 3 o r t & i d u c i a l ' 0 ! - ! 8 x x - ! 8 - ) . x 3 % ! 4 ) . ' 0 , ! . % - ! 8 ! " ? - # ! - ? " # # # - i d d l e o f 0 a c k a g e s % d g e s 0 a c k a g e / r i e n t a t i o n - a r k ! " a d 5 n i t - a r k i n g " 5 - $ u m m y 0 a d s w i t h o u t " a l l ? ? 3 o l d e r b a l l d i a m e t e r r e f e r s t o p o s t r e f l o w c o n d i t i o n 0 r e r e f l o w d i a m e t e r i s m m
internet data sheet rev. 1.2, 2007-04 32 04112007-fhbx-o8hd hyb25dc512[80/16]0b[e/f] double-data-rate sdram figure 1 chip configuration pg-tsopii-66 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 2 pin configuration for x8 organizatio n, pg-tfbga-60, top view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 3 pin configuration for x16 organizati on, pg-tfbga-60, top view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 4 ac output load circuit diagram / timing reference load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 5 package outline pg-tsopii-66 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 6 package outline p(g)-tfbga-60 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 list of figures
internet data sheet rev. 1.2, 2007-04 33 04112007-fhbx-o8hd hyb25dc512[80/16]0b[e/f] double-data-rate sdram table 1 performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 table 2 ordering information for lead-free products (rohs compliant). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 table 3 ball configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 table 4 abbreviations for pin type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 5 abbreviations for buffer type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 6 ball configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 7 abbreviations for pin type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 8 abbreviations for buffer type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 9 mode register definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 10 burst definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 11 extended mode register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 12 truth table 1a: commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 13 truth table 1b: dm operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 14 truth table 2: clock enable (cke). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 15 truth table 3: current state bank n - command to bank n (same bank) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 16 truth table 4: current state bank n - command to bank m (different bank). . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 17 truth table 5: concurrent auto precharge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 18 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 19 input and output capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 20 electrical characteristics and dc operating conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 21 ac operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 22 ac timing - absolute specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 23 i dd conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 24 i dd specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 list of tables
internet data sheet rev. 1.2, 2007-04 34 04112007-fhbx-o8hd hyb25dc512[80/16]0b[e/f] double-data-rate sdram 1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.1 configuration of pg-tsopii-66 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.2 configuration of pg-tfbga-60 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.1 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.2 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 list of figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 list of tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table of contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table of contents
edition 2007-04 published by qimonda ag gustav-heinemann-ring 212 d-81739 mnchen, germany ? qimonda ag 2007. all rights reserved. legal disclaimer the information given in this internet data sheet shall in no ev ent be regarded as a guarantee of conditions or characteristics (?beschaffenheitsgarantie?). with respect to any examples or hi nts given herein, any typical values stated herein and/or any information regarding the application of the device, qimonda hereby disclaims any and all warranties and liabilities of any kin d, including without limitation warranties of non-infringem ent of intellectual property rights of any third party. information for further information on technology, delivery terms and conditio ns and prices please contact your nearest qimonda office. warnings due to technical requirements components may contain dangerous substances. for information on the types in question please contact your nearest qimonda office. qimonda components may only be used in life-support devices or systems with the express writte n approval of qimonda, if a failure of such components can reasonably be expected to cause the failure of that life-support devi ce or system, or to affect the safety or effectiveness of that device or system. life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. if they fail, it is re asonable to assume that the he alth of the user or other persons may be endangered. www.qimonda.com internet data sheet

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